So, are you writing hardware-accelerated .NET apps for satellites yet? (Yep, this is one of the things Hastlayer makes possible!)

We recognized that building a business model of Hastlayer where we license closed-source software goes against our DNA. It's not something that aligns with how we work otherwise, we don't like it, and it doesn't go as smoothly as it can with open-source. So, back to what we believe in the most: Great software, out in the open.

If you want Hastlayer to support new hardware devices (FPGAs), then we have good news too: The Hastlayer Timing Tester app is now open-source as well. You can use this to create the timing values required for hardware designs, which is at the core of creating a driver for a new device.

Do you want to deep dive into the magic of what makes Hastlayer tick? Just head over to the SDK repository! We're really excited to see where you, the development community, will steer Hastlayer!

Note that you need to include your e-mail address in the questionnaire. Then we'll also get back to you personally to address your feedback and you'll take part in a draw where we'll raffle off a device that you can use Hastlayer with, a Nexys A7-100T FPGA board worth $265!

It's just a single-page survey! It closes on 31 January 2020, so be sure to send it in today here!

At one point a small and brave team at Microsoft thought about using FPGAs to accelerate Bing searches. This experiment proved to be a success, and thus the Project Catapult was born. Later these Catapult FPGAs found their way into all Microsoft datacenters, being used first for networking tasks and then also to build a Machine Learning accelerator, Project Brainwave.

Due to its availability on Windows Catapult picked our interest and we started to make Hastlayer compatible with it. After the small development board that Hastlayer initially supported this was promising to be a huge leap in performance - but also a much harder task to complete than we initially thought. With the help of Andrew Putnam and others from Microsoft Research, and the Texas Advanced Computing Center, where Catapult nodes are available, we eventually got it done: Now it's ready and you can use these powerful FPGAs too! Everything you need to know is written in the getting started guide of the SDK.

Catapult is not the only thing that ships with this release, however: there are a wealth of other shiny new parts of Hastlayer for you to check out. There are several new examples (also a Monte Carlo simulation and one written in F#), new pseudo-random number generators, tons of performance improvements and bugfixes. Check out the full release notes on GitHub.

What are you gonna build if you have the power of bare metal hardware?

We'll use the support Hastlayer receives to improve the platform in a way it's most beneficial to you. So let us know what you miss from Hastlayer the most: just open an issue on GitHub or drop us a line!

Update: In the meantime, we got interviewed for CORDIS.

Basic operations can take a various amounts of time on the hardware that Hastlayer generates. Some operations are fast and take less than a clock cycle (like adding two 8b integers) while some other operations take more than one (like multiplying two 32b integers). Hastlayer can calculate how long an operation (or rather, a chain of operations) will take, and thus can create the best suitable hardware implementation: It will pack as many operations as possible into a single clock cycle. This is one of the reasons behind the hardware implementation's improved clock cycle (and power) efficiency: Even without parallel execution a lot can happen in a single clock cycle.

How long operations take is based on hardware timing values. With this release we've updated these values after improving how we measure them. The result is that while in certain cases hardware execution will be slightly slower (and in some cases slightly faster) in all cases it will be more reliable: While previously it could happen that the hardware implementation gave a wrong result due to timing issues, now this should be very rare. As a cherry on top most hardware implementations now use fewer resources on the FPGA, so you can fit more logic onto the same chip.

You can grab the new version from GitHub, or if you have the SDK repository cloned, just pull the changes.

We hope you'll see your Hastlayer hardware implementations fly even better now! And if you have any issues, get in touch with us!

Now there is no paperwork to frighten you any more :). Create a Hastlayer app today!

• Binary operator expressions (like 1 + 2) could in some cases give incorrect results, as could remainder operations (e.g. 9 % 4). These are all fixed now.
• When you try to transform a piece of code with Hastlayer which Hastlayer doesn't support now better error messages will be surfaced, hinting you what exactly the problem is.
• And there is also a new Loopback sample that just sends back what you send it from the host PC. This is to test connectivity and use as a generic testbed.

Hope you'll like these! We've been working on features too, for example adding floating point support, which is mostly done now. We'll talk about it at various conference, starting with ones in Singapore this week!

• Hastlayer now supports method inlining. Method inlining is when a compiler basically copies the implementation of the method to the place where it's called, thus avoiding the overhead of a method call but making the program bigger. We've added support for the AggressiveInlining attribute so you can instruct Hastlayer to inline methods, just as you'd do the same with the .NET compiler. Since method calls in hardware are also an overhead you can vastly improve the performance of your Hastlayer-using code if it contains many small methods that are frequently called. In our tests with the posit floating point type we cut down execution time by about 40%!

• Added a 64b fixed-point arithmetic library and made it Hastlayer-compatible. Why is this good? Although making computations with integers is very efficient (and fast), sometimes you need to use fractions. Before the only option with Hastlayer was to scale up your floating point numbers (multiplying them by 10000 for example so there will be no digits after the decimal point), let Hastlayer do the work, then scale them back down. But now we added a 64b number type that can also handle fractions, it's just that there are 31 bits for the digits before the decimal point and 32 bits for the ones after it. But still, the computations will be quite efficient. Nevertheless we're also working on floating point support.
• Added support for ref and out parameters and made configuration of parallelized code a bit easier.

So Hastlayer just got a lot better for a lot of programs!

For more details and the corresponding downloads visit the Hastlayer SDK and Hastlayer Hardware Framework - Xilinx repos on GitHub. Be sure to also check out the updated documentation on how to utilize these new features.

Also, don't forget that the Hastlayer World Tour is still on with three events coming up!

• Hastlayer goes on a World Tour! If you attend a .NET-related meetup somewhere then there's a good chance we'll showcase Hastlayer there too!
• Version 1.0.6 is released with some important debug improvements and bugfixes.
• While Hastlayer lacks floating point support we've been working on it for a while. While we've implemented a proof of concept for Unums it turned out to be less then ideal. It's an interesting concept but for now we won't pursue it as the core of Hastlayer floating point support and instead we'll implement Posits. With this we'll have float and double-like, but better floating point support shortly.
• Some new Hastlayer videos uploaded to YouTube.

We'll showcase the magic under the title "Turning software into computer chips - Hastlayer" on day 2 (20 September) at 17:00 UTC. It's really exciting to share Hastlayer with all the fellow .NET developers out there!

See you at .NET Conf! You can check out the full agenda as well, there are many interesting talks coming.

Organized by various groups within IEEE (that needs no introduction as the world's largest engineering organization) the International Symposium on Nanoelectronic and Information Systems was focused mostly on electronics in various computer systems. It was hosted by the university of ABV-IIITM where the IT student also commonly specialize in creating FPGA and VLSI circuits. Hastlayer was one of the sessions touching on software development while keeping the connection with logic hardware design.

After IEEE SMC this was the second IEEE event Hastlayer was a part of!

Just comment your questions/remarks here or below the video. Get in touch with us if you could use Hastlayer!

IEEE is one of the world's most famous and renowned (as well as largest) technical professional organization that needs no introduction. IEEE's Systems, Man, and Cybernetics Society (SMC) held its annual conference in October in Budapest, Hungary. Showing the weight of the event even the President and CEO of IEEE itself, Barry L. Shoop, was attending.

A lot of people came to our table to see what Hastlayer is and what is it good for. We're looking forward to the fruitful partnerships that will come out of all of these new connections!