New timing values and why you should care - Hastlayer v1.0.10 released


New timing values and why you should care - Hastlayer v1.0.10 released

Tags: Release, Timing

Today we've released v1.0.10 of Hastlayer. This is mostly a bugfix release, but there is one important detail we've changed: Timing values. What are timing values and why is this a good thing?

Basic operations can take a various amounts of time on the hardware that Hastlayer generates. Some operations are fast and take less than a clock cycle (like adding two 8b integers) while some other operations take more than one (like multiplying two 32b integers). Hastlayer can calculate how long an operation (or rather, a chain of operations) will take, and thus can create the best suitable hardware implementation: It will pack as many operations as possible into a single clock cycle. This is one of the reasons behind the hardware implementation's improved clock cycle (and power) efficiency: Even without parallel execution a lot can happen in a single clock cycle.

How long operations take is based on hardware timing values. With this release we've updated these values after improving how we measure them. The result is that while in certain cases hardware execution will be slightly slower (and in some cases slightly faster) in all cases it will be more reliable: While previously it could happen that the hardware implementation gave a wrong result due to timing issues, now this should be very rare. As a cherry on top most hardware implementations now use fewer resources on the FPGA, so you can fit more logic onto the same chip.

You can grab the new version from GitHub, or if you have the SDK repository cloned, just pull the changes.

We hope you'll see your Hastlayer hardware implementations fly even better now! And if you have any issues, get in touch with us!

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