Working with Hastlayer
Using Hastlayer aims to be an experience as seamless as possible, for software developers not having any FPGA design knowledge. The general process of utilizing Hastlayer to convert a piece of software into an FPGA-implemented hardware that delivers the same logic is as following:
- A performance-critical part of the software is factored out to a separate assembly (class library).
- The Hastlayer class library is added to the software and configured.
- Method calls to the performance-critical component are changed to go through Hastlayer. This makes it possible to direct calls to the hardware implementation when it’s ready but keep the option to run the standard software assembly if e.g. an FPGA is not present.
- The conversion of the performance-critical assembly is done by Hastlayer: VHDL code is generated which is put into the Hastlayer hardware framework, then synthesized and used to program a connected FPGA with the existing vendor toolchain.
- Method calls are now directed to the FPGA and are executed by logic circuits.
- The result of the process is then passed back to the software components calling the methods and then the software continues its execution the regular way.
The prototype readily accelerates selected algorithms by multiple orders of magnitude. This is still in a constrained environment, further improvements are needed and technological challenges have to be solved for Hastlayer to be industrially usable.